? semiconductor components industries, llc, 2009 november, 2009 ? rev. 4 1 publication order number: NB7V32M/d NB7V32M 1.8v / 2.5v, 10ghz 2 clock divider with cml outputs multi ? level inputs w/ internal termination description the NB7V32M is a differential 2 clock divider with asynchronous reset. the differential clock inputs incorporate internal 50 termination resistors and will accept lvpecl, cml and lvds logic levels. the NB7V32M produces a 2 output copy of an input clock operating up to 10 ghz with minimal jitter. the reset pin is asserted on the rising edge. upon power ? up, the internal flip ? flops will attain a random state; the reset allows for the synchronization of multiple NB7V32M?s in a system. the 16 ma differential cml output provides matching internal 50 termination which guarantees 400 mv output swing when externally receiver terminated with 50 to v cc . the NB7V32M is the 1.8 v/2.5 v version of the nb7l32m (2.5 v/3.3 v) and is offered in a low profile 3 mm x 3 mm 16 ? pin qfn package. the NB7V32M is a member of the gigacomm ? family of high performance clock products. application notes, models, and support documentation are available at www.onsemi.com . features ? maximum input clock frequency > 10 ghz, typical ? random clock jitter < 0.8 ps rms ? 200 ps typical propagation delay ? 35 ps typical rise and fall times ? differential cml outputs, 400 mv peak ? to ? peak, typical ? operating range: v cc = 1.71 v to 2.625 v with gnd = 0 v ? internal 50 input termination resistors ? qfn ? 16 package, 3 mm x 3 mm ? ? 40 c to +85 c ambient operating temperature ? these are pb ? free devices a = assembly location l = wafer lot y = year w = work week = pb ? free package (note: microdot may be in either location) *for additional marking information, refer to application note and8002/d. marking diagram* qfn ? 16 mn suffix case 485g http://onsemi.com see detailed ordering and shipping information in the package dimensions section on p age 8 of this data sheet. ordering information 1 nb7v 32m alyw 16 1 figure 1. simplified logic diagram q q reset 2 50 50 clk vtclk clk vtclk vrefac r
NB7V32M http://onsemi.com 2 vrefac gnd gnd gnd vcc r vcc vcc vcc q q vcc vtclk clk clk 5678 16 15 14 13 12 11 10 9 1 2 3 4 NB7V32M exposed pad (ep) figure 2. pin configuration (top view) vtclk table 1. truth table clk clk r q q x x h l h z w l clk 2 clk 2 z = low to high transition w = high to low transition x = don?t care table 2. pin description pin name i/o description 1 vtclk ? internal 50 termination pin for clk 2 clk lvpecl, cml, lvds input non ? inverted differential clk input. (note 1) 3 clk lvpecl, cml, lvds input inverted differential clk input. (note 1) 4 vtclk ? internal 50 termination pin for clk 5 vrefac ? internally generated output voltage reference for capacitor ? coupled inputs, only 6 gnd ? negative supply voltage 7 gnd ? negative supply voltage 8 gnd ? negative supply voltage 9 vcc ? positive supply voltage. (note 2) 10 q cml output inverted differential output 11 q cml output non ? inverted differential output 12 vcc ? positive supply voltage. (note 2) 13 vcc ? positive supply voltage. (note 2) 14 vcc ? positive supply voltage. (note 2) 15 r lvcmos input asynchronous reset input. internal 75 k pulldown to gnd. 16 vcc ? positive supply voltage. (note 2) ? ep ? the exposed pad (ep) on the qfn ? 16 package bottom is thermally connected to the die for im- proved heat transfer out of package. the exposed pad must be attached to a heat ? sinking con- duit. the pad is electrically connected to the die, and must be electrically and thermally connected to gnd on the pc board. 1. in the diffe rential configuration when the input termination pins (vtclk, vtclk ) are connected to a common termination voltage or left open, and if no signal is applied on clk/clk input, then the device will be susceptible to self ? oscillation. q/q outputs have internal 50 source termination resistors. 2. vcc and gnd pins must be externally connected to a power supply for proper operation.
NB7V32M http://onsemi.com 3 table 3. attributes characteristics value esd protection human body model machine model > 4 kv > 200 v moisture sensitivity 16 ? qfn level 1 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 164 meets or exceeds jedec spec eia/jesd78 ic latchup test for additional information, see application note and8003/d. table 4. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc positive power supply gnd = 0 v 3.0 v v in positive input voltage gnd = 0 v 1.89 v v inpp differential input voltage |d ? d | 1.89 v i in input current through r t (50 resistor) 40 ma i out output current through r t (50 resistor) 40 ma i vrefac vrefac sink/source current 1.5 ma t a operating temperature range ? 40 to +85 c t stg storage temperature range ? 65 to +150 c ja thermal resistance (junction ? to ? ambient) (note 3) 0 lfpm 500 lfpm qfn ? 16 qfn ? 16 42 35 c/w c/w jc thermal resistance (junction ? to ? case) (note 3) qfn ? 16 4 c/w t sol wave solder pb ? free 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 3. jedec standard multilayer board ? 2s2p (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
NB7V32M http://onsemi.com 4 table 5. dc characteristics positive cml output v cc = 1.71 v to 2.625 v; gnd = 0 v; t a = ? 40 c to 85 c (note 4) symbol characteristic unit min typ max power supply current i cc power supply current (inputs and outputs open) v cc = 2.5 v 5% v cc = 1.8 v 5% 90 80 100 90 ma cml outputs v oh output high voltage (note 5) v cc = 2.5 v v cc = 1.8 v v cc ? 30 2470 1770 v cc ? 1 2490 1790 v cc 2500 1800 mv v ol output low voltage (note 5) v cc = 2.5 v v cc = 2.5 v v cc ? 600 1900 v cc ? 500 2000 v cc ? 400 2100 mv v cc = 1.8 v v cc = 1.8 v v cc ? 550 1250 v cc ? 450 1350 v cc ? 350 1450 differential inputs driven single ? ended (note 6) (figures 5 and 7) v th input threshold reference voltage range (note 7) 1050 v cc ? 100 mv v ih single ? ended input high voltage v th + 100 v cc mv v il single ? ended input low voltage gnd v th ? 100 mv v ise single ? ended input voltage (v ih ? v il ) 200 1200 mv vrefac v refac output reference voltage @ 100 a for capacitor ? coupled inputs, only v cc = 2.5 v (note 8) v cc = 1.8 v v cc ? 850 v cc ? 750 v cc ? 500 v cc ? 450 mv differential inputs driven differentially (figures 6 and 9) (note 9) v ihd differential input high voltage 1100 v cc mv v ild differential input low voltage gnd v cc ? 100 mv v id differential input voltage (v ihd ? v ild ) 100 1200 mv v cmr input common mode range (differential configuration, note 10) (fig- ure 9) 1050 v cc ? 50 mv i ih input high current (vtclk/vtclk open) ? 150 150 ua i il input low current (vtclk/vtclk open) ? 150 150 ua control input (reset pin) v ih input high voltage for control pin v cc ? 200 v cc mv v il input low voltage for control pin gnd 200 mv i ih input high current ? 150 150 ua i il input low current ? 150 150 ua termination resistors r tin internal input termination resistor (@ 10 ma) 45 50 55 r tout internal output termination resistor (@ 10 ma) 45 50 55 note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 4. input and output parameters vary 1:1 with v cc . 5. cml outputs loaded with 50 to v cc for proper operation. 6. v th , v ih , v il and v ise parameters must be complied with simultaneously. 7. v th is applied to the complementary input when operating in single ? ended mode. 8. v refac will not be less than gnd + 1050 mv. 9. v ihd , v ild, v id and v cmr parameters must be complied with simultaneously.
NB7V32M http://onsemi.com 5 10. v cmr min varies 1:1 with gnd, v cmr max varies 1:1 with v cc . the v cmr range is referenced to the most positive side of the differential input signal. table 6. ac characteristics v cc = 1.71 v to 2.625 v; gnd = 0 v; t a = ? 40 c to 85 c (note 11) symbol characteristic min typ max unit f max maximum input clock frequency 10 ghz v outpp output voltage amplitude (@ v inppmin ) f in 10ghz (note 12) (figure 3) 280 400 mv t plh , t phl propagation delay to differential outputs, @ 1 ghz, measured at differential cross ? point clk/clk to q, q r to q, q 150 200 200 275 ps t plh tc propagation delay temperature coefficient 50 fs/ c t skew duty cycle skew (note 13) device ? device skew (t pdmax ? t pdmin ) 20 50 ps t rr reset recovery (see figure 11) 300 135 t pw minimum pulse width r 500 200 t dc output clock duty cycle (reference duty cycle = 50%) f in 10 ghz 45 50 55 % t jitter rj ? output random jitter (note 14) f in 10 ghz 0.2 0.8 ps rms v inpp input voltage swing (differential configuration) (figure 10) (note 15) 100 1200 mv t r, t f output rise/fall times @ 1 ghz (20% ? 80%), q, q 35 60 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 11. measured using a 1 ghz, v inpp min, 50% duty ? cycle clock source. all output loading with external 50 to v cc . input edge rates 40 ps (20% ? 80%). 12. output voltage swing is a single ? ended measurement operating in differential mode. 13. duty cycle skew is defined only for differential operation when the delays are measured from cross ? point of the inputs to the cross ? point of the outputs. duty cycle skew is measured between differential outputs using the deviations of the sum of t pw ? and t pw+ @ 1 ghz. skew is measured between outputs under identical transitions and conditions. 14. additive rms jitter with 50% duty cycle clock signal. 15. input voltage swing is a single ? ended measurement operating in differential mode. figure 3. clock output voltage amplitude (v outpp ) vs. input frequency (f in ) at ambient temperature (typ) fin, clock input frequency (ghz) output voltage amplitude (mv) 500 450 400 350 300 200 q amp (mv) figure 4. input structure 50 50 clk v cc vtclk vtclk 250 0246810 clk r c r c i
NB7V32M http://onsemi.com 6 clk v th clk v th figure 5. differential input driven single ? ended v ih v il v ihmax v ilmax v ih v th v il v ihmin v ilmin v cc v thmax v thmin gnd v th clk clk v ildmax v ihdmax v ihdtyp v ildtyp v ihdmin v ildmin v cmr gnd v id = v ihd ? v ild v cc clk clk q q t plh t phl v outpp = v oh (q) ? v ol (q) v inpp = v ih (clk) ? v il (clk) v ihd v ild v id = |v ihd(clk) ? v ild(clk)| clk clk figure 6. differential inputs driven differentially figure 7. v th diagram figure 8. differential inputs driven differentially figure 9. v cmr diagram figure 10. ac reference measurement clk clk v cmmax v cmmin figure 11. ac reference measurement (timing diagram) t phl t plh t rr(min) 50% 50% 50% 50% 50% q clk r v outpp = v oh (q) ? v ol (q) v inpp = v ih (clk) ? v il (clk)
NB7V32M http://onsemi.com 7 lvpecl driver v cc v ee z o = 50 v th = v cc ? 2 v z o = 50 NB7V32M clk 50 50 clk v ee figure 12. lvpecl interface lvds driver v cc gnd z o = 50 z o = 50 NB7V32M 50 50 gnd figure 13. lvds interface v cc v cc figure 14. standard 50 load cml interface figure 15. capacitor ? coupled differential interface (v tclk /v tclk connected to v refac ; v refac bypassed to ground with 0.1 f capacitor) figure 16. capacitor ? coupled single ? ended interface (v tclk /v tclk connected to v refac ; v refac bypassed to ground with 0.1 f capacitor) v tclk v tclk clk clk v tclk v tclk cml driver v cc gnd z o = 50 v t = v t = v cc z o = 50 NB7V32M 50 50 gnd v cc clk clk v tclk v tclk v cc differential driver v cc gnd z o = 50 v th = v refac z o = 50 NB7V32M 50 50 gnd v cc clk clk v tclk v tclk v th v tclk v tclk v th single ? ended driver v cc gnd z o = 50 v th = v refac NB7V32M 50 50 gnd v cc clk clk v th
NB7V32M http://onsemi.com 8 figure 17. typical cml output structure and termination v cc 50 50 16 ma 50 50 v cc (receiver) gnd NB7V32M receiver q q driver device receiver device qd figure 18. typical termination for cml output driver and device evaluation q d v cc 50 50 z = 50 z = 50 dut ordering information device package shipping ? NB7V32Mmng qfn ? 16 (pb ? free) 123 units / rail NB7V32Mmntxg qfn ? 16 (pb ? free) 3000 / tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
NB7V32M http://onsemi.com 9 package dimensions 16 pin qfn case 485g ? 01 issue d 16x seating plane l d e 0.15 c a a1 e d2 e2 b 1 4 58 12 9 16 13 notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b applies to plated terminal and is measured between 0.25 and 0.30 mm from terminal. 4. coplanarity applies to the exposed pad as well as the terminals. 5. l max condition can not violate 0.2 mm minimum spacing between lead tip and flag ??? ??? ??? b a 0.15 c top view side view bottom view pin 1 location 0.10 c 0.08 c (a3) c 16 x e 16x note 5 0.10 c 0.05 c a b note 3 k 16x dim min max millimeters a 0.80 1.00 a1 0.00 0.05 a3 0.20 ref b 0.18 0.30 d 3.00 bsc d2 1.65 1.85 e 3.00 bsc e2 1.65 1.85 e 0.50 bsc k l 0.30 0.50 exposed pad 0.18 typ l1 detail a l alternate terminal constructions ?? ?? 0.00 0.15 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* mm inches scale 10:1 0.50 0.02 0.575 0.022 1.50 0.059 3.25 0.128 0.30 0.012 3.25 0.128 0.30 0.012 exposed pad on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada japan : on semiconductor, japan customer focus center 2 ? 9 ? 1 kamimeguro, meguro ? ku, tokyo, japan 153 ? 0051 phone : 81 ? 3 ? 5773 ? 3850 NB7V32M/d the products described herein (NB7V32M), may be covered by u.s. patents including 6,362,644 . there may be other patents pending. gigacomm is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : http://onsemi.com order literature : http://www.onsemi.com/litorder for additional information, please contact your local sales representative.
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